With the development of manufacturing technology of semiconductor devices, integrated circuits with higher performance and more functionalities require greater element density, smaller spaces between various components and elements, and smaller dimensions and sizes for individual elements. Hence the control over processes is quite stringent during manufacturing processes of semiconductor devices.
Semiconductor devices achieve greater integration degree through proportional scaling down, and the channel length of a MOS transistor is also shortened proportionally. However, when the channel length of the MOS transistor becomes very short, the so-called Short Channel Effects (SCsE) and the Drain-Induced Barrier Lowering (DIBL) effect may set serious obstacles for miniaturization of semiconductor devices.
Due to the fact that Short Channel Effects (SCEs) may lower device performance and even cause failure of devices, thus reducing SCEs is an important issue in the research and manufacturing of semiconductor devices. Internal mechanical stress of semiconductor devices is widely used to adjust performance of devices. SCEs can be improved by applying a stress to the channel.
Usually the method of applying a stress may manipulate in the source/drain (S/D) regions in order to form tensile or compressive stress. For example, in general silicon technology, the transistor channel is oriented along the silicon {110 }. In this configuration, when compressive stress is applied to the channel along the channel length direction and/or tensile stress is applied to the channel along the direction perpendicular to the channel, mobility of holes will increase; whereas when tensile stress is applied to the channel along the channel length direction and/or compressive stress is applied to the channel along the direction perpendicular to the channel, mobility of electrons will increase. Therefore introducing stress into channel regions of semiconductor devices can enhance device performance.
Using Silicon On Insulator (SOI) substrate in place of silicon substrate may also achieve the effects of reducing SCE and enhancing device performance. SOI technology introduces a buried oxide layer between the top silicon layer and the substrate bulk silicon layer. By forming a semiconductor film on an insulator, SOI materials possess some incomparable advantages over bulk silicon: dielectric isolation of components in integrated circuits can be achieved so as to eliminate the parasitic latch-up effect in bulk silicon CMOS circuits; and integrated circuits made of these materials have multiple advantages such as small parasitic capacitance, high integration density, high speed, simple processes and reduced SCE, and are especially suitable for low voltage and low power consumption circuits. Therefore, SOI may become a mainstream technology for deep sub-micron low voltage and low power consumption integrated circuits.
At the same time, the heterostructure of SOI provides opportunities for the construction of ultra-thin silicon bulk devices. Ultra-thin SOI provides an option for controlling Short Channel Effects by the electrostatic barrier established by the silicon-dielectric interface.
Currently, there exists a technique that a ground layer is formed in the ultra-thin BOX layer of an ultra-thin SOI MOS transistor (Ultrathin-SOI MOSFET) to reduce Short Channel Effects (SCE), and to control power consumption. However, it is very difficult to apply a larger stress to such devices so as to improve device performance.